1. Field of the Invention
The present invention relates generally to methods and materials for forming patterned layers within integrated circuits. More particularly, the present invention relates to methods and materials for forming damage free patterned layers adjoining the edges of high step height apertures within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed transistors, resistors, diodes and other electrical circuit elements. These electrical circuit elements are interconnected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by insulator layers.
Within the context of the multi-step method by which integrated circuit chips are formed from semiconductor substrates within and upon whose surfaces are formed integrated circuits, there exist two discrete process steps at the end of the method. The two discrete process steps are: (1) the final conductor metallization process step whereby final conductor bonding pad layers are formed, in part, around the periphery of an integrated circuit to provide locations for connection to electrical circuits and electrical circuit elements external to the integrated circuit, and (2) the scribing and parting process step whereby a semiconductor substrate having discrete integrated circuits formed within and upon its surface is divided into discrete integrated circuit chips.
It is common in the art of integrated circuit manufacture for the final conductor metallization process and the scribing and parting process to be intertwined. In particular, it is common for: (1) semiconductor substrates to be scribed prior to forming upon those semiconductor substrates final conductor bonding pad layers, and (2) semiconductor substrates to be parted after forming upon those semiconductor substrates final conductor bonding pad layers. Such an ordering of process steps typically provides for significant reductions in physical stress within the semiconductor substrate from which is formed the integrated circuit chips while simultaneously providing economy in manufacturing and ease of alignment of photolithographic masks upon the semiconductor substrate.
As a separate consideration with regard, in general, to photolithographic processes by which conductor layers are patterned within semiconductor substrates, it is also recognized in the art that photoresists employed in those photolithographic processes often suffer from inhomogeneous standing wave photo-exposures when those photoresists are photo-exposed directly upon a highly reflective conductor metal layer such as aluminum or an aluminum alloy conductor metal layer. In order to provide homogeneous photo-exposure of the photoresists formed upon a highly reflective conductor metal layer, Anti-Reflective Coating (ARC) layers are often formed upon the top surface of the highly reflective conductor metal layer. The use of such Anti-Reflective Coatings (ARCs) is in general disclosed by S. Wolf et al. in Silicon Processing for the VLSI Era, Volume 1: Process Technology, (Lattice Press: Sunset Beach, Calif.) (1986) pg. 441. Commonly, although not exclusively, a titanium nitride layer is employed as an Anti-Reflective Coating (ARC) layer.
By virtue of the ordering of the process steps associated with the scribing process, the parting process and the final conductor bonding pad metallization process, along with the materials employed within those processes, an integrated circuit structure similar to the integrated circuit structure illustrated in FIG. 1 is common in the art.
Shown in FIG. 1 is a semiconductor substrate 10 having scribed into its surface a kerf of width W1 and depth D1, which kerf separates portions of the semiconductor substrate 10 which are to be parted into separate integrated circuit chips. Formed conformally upon the semiconductor substrate 10 and conformally into the kerf is a blanket final conductor layer 12, and formed upon the blanket final conductor layer 12 is a blanket conformal Anti-Reflective Coating (ARC) layer 14 which has an aperture of width W2 and depth D2 formed therein at the location upon the semiconductor substrate 10 where the blanket final conductor layer 12 is formed into the kerf. Formed upon the surface of the blanket conformal Anti-Reflective Coating (ARC) layer 14 is a blanket photoresist layer 16. Due to the visco-elastic properties of the photoresist material from which is formed the blanket photoresist layer 16, the blanket photoresist layer 16 is thinner upon portions of the semiconductor substrate 10 near the edges of the kerf than upon other portions of the semiconductor substrate 10.
Shown in FIG. 2 and FIG. 3 are the results of further processing of the semiconductor substrate 10 whose structure is illustrated in FIG. 1. Shown in FIG. 2 is the patterning of the blanket photoresist layer 16 to yield the patterned photoresist layers 16a, 16b, 16c and 16d. The patterned photoresist layers 16a and 16d are typically employed as an etch mask in forming patterned final conductor bonding pads layers upon the surface of the semiconductor substrate 10. The patterned photoresist layers 16b and 16c are typically employed as an etch mask in forming patterned final conductor seal ring layers upon the surface of the semiconductor substrate 10. As is shown in FIG. 2 the patterned photoresist layers 16b and 16c are significantly shorter in height than the patterned photoresist layers 16a and 16d, since the patterned photoresist layers 16b and 16c are formed from the thinner portions of the blanket photoresist layer 16 closer to the kerf.
Shown in FIG. 3 are the results of etching of the exposed portions of the blanket final conductor layer 12 and the blanket conformal Anti-Reflection Coating (ARC) layer 14 to form: (1) the patterned conformal Anti-Reflective Coating (ARC) layers 14a, 14b, 14c and 14d; (2) the patterned final conductor bonding pad layers 12a and 12d; and, (3) the patterned final conductor seal ring layers 12b and 12c. During the etching processing, portions of the patterned photoresist layers 16a, 16b, 16c and 16d are eroded by the etchant, which is typically a Reactive Ion Etch (RIE) etchant gas mixture. Since the patterned photoresist layers 16b and 16c are shorter in height than the patterned photoresist layers 16a and 16d, the erosion process more rapidly consumes the patterned photoresist layers 16b and 16c to yield the etched patterned photoresist layers 16b' and 16c', leading to over-etching of the patterned conformal Anti-Reflective Coating (ARC) layers 14b and 14c, and possibly also the patterned final conductor seal ring layers 12b and 12c. Such over-etching provides surfaces to which functional and reliable seals and connections may be difficult to establish. It is thus towards the specific goal of forming damage free patterned final conductor layers adjoining the edges of high step height kerfs within semiconductor substrates that the present invention is specifically directed.
The foregoing description provides a specific example of the problem towards which the present invention is directed. In more general terms, the present invention is also directed towards providing a method whereby damage free patterned layers may be formed adjoining the edges of high step height apertures within integrated circuits. The method provided by the present invention has broader applicability than forming only damage free patterned final conductor layers adjoining the edges of high step height kerfs within semiconductor substrates.